The present invention relates to a dataflow processor having a plurality of computing modules connected to a ring bus.
In conventional dataflow processors, a packet comprising data bits and additional tag bits specifying the type of computation to be performed thereon is forwarded onto a ring bus to which a plurality of computing modules are connected. Each computing module includes a bus interface that inspects the contents of the tag to determine that the packet is destined to the own module. A queuing circuit is provided to assemble packets destined to the own module to form a data set. A computing logic receives the data set and performs a particular computation specified by the tag and forwards the result of the computation back to the ring bus through the bus interface with a tag appended to it for further computations by other computing modules.
It has been desired to process both double precision data and single precision data on a dataflow processor to take advantage of its high speed capability. Since double precision data has twice as much bit width as that of single precision data, all components of a single-precision dataflow processor must be doubled to handle the double precision data. In particular, the bus interface of each computing module usually comprises buffers for interfacing between the ring bus and the components of the module. If a single precision dataflow processor is redesigned to handle double precision data as well as single precision data, the storage capacity of the buffers of the interface must be doubled. This substantially increases the amount of hardware of the dataflow processor.